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Abstract
The main purpose of this thesis is to study the Serial Advanced Technology Attachment
(SATA) system which applies high-speed serial data transfer rate between a storage
device and a host controller.
The SATA protocol has been studied and a hardware architecture of the SATA host
controller is proposed. Different encoding, scrambling, error detection, and data
synchronization techniques were studied and the proposed architecture was modeled
and implemented in Verilog.
The SATA host controller architecture has been verified in three testing phases: Unit
testing, integration testing, and system testing. Testing scenarios that verify the basic
SATA protocol and its corner cases are developed. Assertion-based verification was
also applied using the Property Specification Language (PSL).
The proposed architecture has been compared to other market designs and proved to
have several advantages. Among them, the architecture targets both FPGA and ASICtechnologies,
includes timing synchronization solutions that mark a good design, and
avoids error-prone coding styles, which greatly reduces RTL design flaws and debug
time necessary to fix any pre- and post-synthesis simulation mismatches.
Moreover, the SATA host controller architecture was synthesized and realized on
Xilinx Virtex II Pro FPGA, achieving the required GEN1 speed of 150 MHz.
Keywords
Serial Advanced Technology Attachment (SATA), Frame Information Structure (FIS),
Cyclic Redundancy Check (CRC), Property Specification Language (PSL), Clock
Domain Crossing (CDC).