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Abstract
Single electron transistors (SETs) were invented as soon as the nanotechnology rose to the surface. SET current shows to have peaks at certain gate voltages. Such current disappears at other gate voltages i.e. current suppression at certain gate voltages, which is unlike to the well known MOS current response. This phenomenon is referred to as coulomb blockade, which is due to coulomb repletion rising from the electrostatic charging energy of what is called the island or quantum dot. Electrons tunnel from source to drain passing through the island in discrete fashion caused by the charge quantization. This adds the capability of controlling electron transport through single electron tunneling and so the device is given its name. The orthodox theory explains electron transport from source to drain employing free energies, tunnel rates and coulomb blockade phenomenon; in addition it considers electron tunneling to be quantized. The tunneling phenomenon is very fast and requires very small amount of energy depending on the change in free energy accompanying electron transport. Being very fast and of low power consumption, the SET
has promised to be valuable in many applications.
The thesis introduces some physical fundamentals dominating the device physical properties such as coulomb blockade, free energy and quantum tunneling. Device structure and its equivalent circuit are then presented with a broad explanation of the orthodox theory of coulomb blockade. Several analog and digital applications and some fabrication techniques are briefly illustrated showing the promising advantages of SET and the validity of production. A comparison between different models for the simulation of SET based on the orthodox theory was comprehensively presented as the master equation and the Monte Carlo simulation algorithm. The recursion relation simulation method is also expansively described in literature showing the implementation issues. Then, a simplified model has been proposed to account for unnecessary lengthy calculation process resulting from the large number of states assumed for simulation. The model was realized on PSPICE and was compared to the recursion relation simulation method. It proved to be faster and still accurate in simulating SET. Taking much less runtime than the available models, the proposed model can easily be used to simulate SET-based integrated circuits on PSPICE. Different SET logic circuits such as logic inverter, NAND gate, OR gate and latch Flip¬Flop were applied and checked. An analog amplifier was also designed and simulated.