الفهرس | Only 14 pages are availabe for public view |
Abstract Test pattern generation is one of the most hot research topics due to its high importance in the industry. Test pattern generation is a crucial step during the quality assurance steps in the fabrication of digital circuits. This thesis represents the work done for generating test patterns for combinational digital circuits described using VHDL. First the behavioral or structural description of the circuit is converted to its equivalent netlist consisting only of logic gates. The second step is to apply the test pattern generation algorithm on the produced netlist in order to generate the required test vectors. Some optimization techniques are applied when converting the VHDL code to its equivalent netlist; also some heuristic measures were used to speed up the ATPG process. This work started by studying the VHDL grammar and extracting some of the synthesizble constructs it has, then an algorithm is applied to convert each of these constructs to its equivalent logic gates and optimising the generated netlist. After getting the netlist, a study was made for available ATPG algorithms that could be used to generate test vectors and the choice was in favour of the PODEM algorithm. Applying the algorithm on the generated netlist generates the required test patterns. To speed up the process of ATPG we used some heuristic measures to guide the algorithm. As a final step, this test was tested on a number of benchmarks to verify its correctness. |