الفهرس 
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Abstract
The digital signal processing (DSP)Technology is nowadays commonplace in such devices as mobile phones, multimedia computers, video recorders,CD players, digital TV and medical electronics. The DSP has a scientific computation, which is not easily represented in fixed-point format due to inherent limitation. The floating-poi nt format is necessary for representing the scientific computation since it represents very small values.
This thesis used FPGA for implementing the floating-point arithmetic modules which can be used in DSP processor.these modules are floating-point multiplier, floating-point adder/subtractor, floating-point multiplier, accumulator (MAC).The simulation and the synthesis results for these modules are presented.the synthesis results for the floating-point multiplier in several floating –point formats, including the IEEE single precision format are given.A comparison of the synthesis results with previously published results is provided. Two new configurations for floating-point multiplier are presented to optimize area and speed.All the modules proposed presented in this thesis support creation of custom format floating-point pipelines.