الفهرس Only 14 pages are availabe for public view
 |  | from | 175 |  |  |
| | | from | 175 | | |
Abstract
Rapid device scaling pushes the dimensions of the field effect transistors to the nanometer regime where quantum effects play an important role in determining the transistor characteristics. The Non-equilibrium Green’s function formalism (NEGF)
provides a rigorous description of quantum transport in nanoscale devices. The Real-Space (RS) representation is the most accurate yet complex representation used in the NEGF. The geometry of fully-depleted double gate (DG) MOSFETs permits the use of a simpler quasi two-dimensional (2D) representation, the mode-space (MS) which is computationally efficient. This thesis addresses the simulation and design of the nanoscale DG MOSFETs using the NEGF framework in both the RS and MS representations. Different transport models in RS will be implemented in the FETMOSS simulator, whose original version was capable of simulating NEGF using the MS only.
In this work, the 2D NEGF simulation methodology and results of DG
MOSFETs using the RS approach are presented. A new computationally efficient method for the NEGF in RS is proposed and implemented in the FETMOSS
simulator. Other methods existing in the literature were studied, implemented and compared with the proposed one. Moreover, the MS validity is examined by comparison with the RS. Then, a fast method to check the MS validity is investigated and implemented and some ideas are suggested to further reduce the MS
computational burden.
Exploiting the 2D quantum simulator built in this work, design and simulation of nanoscale DG MOSFET at the end of the International Technology Roadmap for Semiconductors (ITRS) is carried. The design of a 10 nm DG MOSFET is presented using a design optimization procedure. For the first time to be reported, the obtained
results show that satisfying both the on-current and the switching speed requirements of the ITRS for the high power device is possible. The use of high-k material gate dielectric for the low standby power 16 nm DG MOSFET is also investigated. Finally, the effect of 2D electrostatics on the nanoscale DG MOSFETs capacitance is studied.