الفهرس 
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Abstract
Recent efforts in the design of integrated circuits for RP communication
transceivers have focused on maximizing the dynamic-range of modem wireless
communication systems, medical equipment, hearing aids, disk drives, and so
on, as well as adaptability to multiple RP communication standards.
The demand for wide-bandwidth and variable gain for telecommunication
applications requires a Variable Gain Amplifier (VGA) in the baseband. The
VGA receives an input signal with wide dynamic-range and continuously tries
to maintain the output signal at a constant level through an Automatic Gain
Control (AGC) loop. The output of the VGA is applied to the Analog-to-Digital
Converter (ADC). The signal level to the ADC should be kept at its maximum
level to achieve optimum SNR. These requirements of wide bandwidth and
input dynamic-range for the VGA should be achieved at reasonable power
dissipation.
Our thesis describes a novel circuit topology for a Programmable Variable
Gain Amplifier (PVGA) as well as output buffer. The PVGA is composed of two
variable gain amplifier stages and an output buffer. It can achieve 400 MHz
bandwidth with 62 dB dynamic-range. Power reduction is developed for the
variable gain amplifier stages and output buffer. The PVGA circuit is designed
and simulated in a 0.13 urn IBM-CMOS process. The simulation results show a
minimum bandwidth of 420 MHz at gain of 50 dB. Such wide bandwidth allows
our proposed PVGA to be used in multi-standard protocols. The variable gain
amplifier achieves a wide dynamic-range of 62 dB. The circuit has a THD of -40
dB at peak-to-peak differential output voltage of 700 m V and frequency 400
MHz. Moreover; the proposed circuit reports a good noise performance; the