الفهرس 
Analog to Digital ConversionOnly 14 pages are availabe for public view
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Abstract
The work of this thesis is dedicated to studying high performance analog-to-digital converter
design. The thesis is divided into four main sections.
In the first section, basic definitions and metrics related to the process of analog to digital
conversion are introduced. Error sources common to all types of ADCs are explained.
Also, a brief overview of a number of different ADC architectures is provided. And finally,
performance trends in recent state-of-the-art ADCs reported in literature are analyzed.
In the second section, the thesis scope is narrowed down to medium-resolution, mediumspeed,
low power ADCs which find use in many wireless communications applications. A
specific type of ADCs, namely, pipeline ADCs is proven to be the best choice for this type
of applications. The converter operation is more closely analyzed. Main sources of errors
in the ADC are identified, and individual circuit level specifications to meet the required
ADC performance are derived. Key system and architecture level choices allowing low
power design are also identified. In the third section, ADC calibration is identified as an
attractive choice for further performance improvement, and power reduction. Pipeline ADC
calibration is studied thoroughly. A survey of different calibration techniques reported in
literature is provided. One specific calibration technique II Split-ADC calibration” proves
to be of significant merit, and is implemented on a system level model for verification.
The technique is shown to demonstrate potential savings in the ADC power consumption;
through reducing the current in the first stage, and correcting for its errors via the digital
calibration algorithm.
In the fourth and final part of this thesis, a specific design example of a lOb, 50Ms/s
pipeline ADC is perused. System level simulations based on a behavioral MATLAB model
taking into account different circuit non-idealities are used to derive individual circuit specifications.
Circuit le~el simulations, on the other hand, are used to verify the overall ADC
performance. The circuit is designed in O.131lm lP7M CMOS technology, consumes a total
power of 6.25 mW, and achieves an SNDR of 58.7 dB at the Nyquist rate. Overall system
functionality across different temperature, voltage, and process corners is verified. Layout for the most critical first pipeline stage is performed, and the circuit exhibits only a slight
deterioration in SNDR after inclusion of the extracted stage parasitics.