الفهرس 
Introduction to Serial Data
’Transversal FilterOnly 14 pages are availabe for public view
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Abstract
This thesis studies equalization techniques for high speed serial data transmission. It
presents the design of a Decision Feedback Equalizer (DFE) both at the system and
circuit levels. The target application is serializer/deserializer (SERDES) working at
a data rate of 10 Gb/s.
A Decision feedback equalizer using half-rate architectures is used. Half-rate architectures
relax the requirements on the buffers speed and the clock skew, since
consequent latches work at two different edges of the clock. The system uses 5 taps;
this number of taps is found to be optimum. Increasing the number of taps enable
the system to remove more lSI components. However, it increases the load on the
summation circuit and the capacitance due to routing, which limits the performance.
An adaptive least mean square (LMS) algorithm is used for tap coefficient calculation.
The system doesn’t use any speculation techniques; speculation techniques
decrease the requirements on the slicer delay which enables the system to work at
higher speeds. However, it increases area and power consumption of the system.
It also increases the load, and complicates the design of other receiver blocks like
the clock data recovery (CDR). New fast slicer architecture is introduced to enable
10Gb/s speed without speculation. This new architecture has higher speed and
better sensitivity; however it consumes larger area and power than the conventional
buffer used for other taps. The multiplication function of DFE system is achieved by
a multiplying digital-to-analog converter (MDAC). The input (uri-equalized signal)
is applied to a differential pair, with degeneration resistor to increase its linearity,
and degeneration capacitor to introduce some high frequency boosting at high fre-
quency. Combining these functionalities into one block decreases the overall delay
and so improves the system performance.
The decision feedback equalizer (DFE) system is designed in a gO-nm CMOS technology.
This design consumes a power of 43m W from 1.2 supply voltage, and area of
177urnX146um. Removing speculation improves power consumption by 60%. Five
test cases for different transmission channel characteristics have been simulated as
a test vehicle. The equalizer is shown to compensate for channel losses up to 22dB
and achieve error-free data recovery.