الفهرس 
INTRODUCTIONOnly 14 pages are availabe for public view
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Abstract
This thesis is devoted to introduce new two approaches to field programmable gate array (FPGA) design and implementation of synchro to digital converter using Co-ordinate Rotation Digital Computer CORDIC algorithm. And design and implementation a fast and accurate CORDIC modulus extractor for radar MTD using field programmable gate array FPGA. CORDIC algorithm was the best replacement of analog conversion system by the high resolution digital. This algorithm used for the fast calculation of elementary functions like multiplication, division, trigonometric functions. The first approach is based on receiving the synchro signals S1, S2, and S3 from the synchro motor, and converts them to two perpendicular signals sin signal and cosine signal using solid state Scott-t transformer. Then the CORDIC circuit receives these signals after converting them to digital and produces the azimuth angle in digital format. This prototype of hardware implementation of CORDIC algorithm used Spartan –III series FPGA, with constraint to area efficiency and throughput architecture. The prototype results show that the conversion time is less than 1µs which is suitable for real time applications in radar and missile control applications. The second approach is based on the Modulus extractor receives real and imaginary part from Doppler filter bank and produces a modulus output suitable for amplitude processing by constant false alarm rate processor CFAR. This implementation contributes a fast propagation delay for this extractor and gives an accurate results for the modulus and angle output. This prototype of hardware implementation of CORDIC algorithm used Spartan –III series FPGA, with constraint to area efficiency and throughput architecture. The extractor results show that the conversion time is with less than 0.025% in angle measurement and 0.9% accuracy in modulus measurement which is suitable for real time applications in radar and missile control applications.