الفهرس 
The Analog Linear Equalizer
Time-Interleaving ConceptOnly 14 pages are availabe for public view
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Abstract
Driven by an accelerating high demand in the interface IPs market for much faster com-munication links, market enormously moved from the parallel I/Os to high-speed serial links. An increasing hunger for more bandwidth appeared in all applications from networking and computers to wireless and consumer Electronic devices. Moreover, the end user has a grow-ing need for faster exchange of data through Internet, watching full HD movies or listening to ultra-pure music using portable devices which should run for enough long time.
Multi-Gbps transceivers are expected to operate error-free for high-performance-based applications, consume as small silicon area and as low power as possible. This imposes new design and optimization challenges that are di cult to meet, especially for a small area, a low power, and a high speed. However, having a single PHY that meets multiple standards reduces the time-to-market of SOC designs. That is why large companies race to build their own multi-standard recon gurable PHYs for new high data-rates and technology nodes.
One way to meet di erent standards is recon gurability, heavily depending on pro-grammability and the digital portion of the system. To make system easily recon gurable we should process the signal digitally as much as we can, that is why ADC-based-receivers come ahead. ADC is utilized to change the signal from the analog domain to the digital domain where we can perform feed-forward equalization or decision-feed-back equalization with a variable number of switchable taps to achieve various ranges of channel equalization and hence meets multi-standard requirements.
The main challenge of the digital receivers is the ADC itself. To get high-data-rates, ADCs are required to be Flash to reach such speeds. Flash architectures are well-known traditionally to have the highest speeds, largest area and highest power dissipation.
This thesis proposes a 20-GS/s low-power ADC-based equalizer for high-speed serial wireline receivers. Digital receivers are recently adopted to overcome the challenges facing circuits in the analog domain such as power, delay, and mismatches, besides exploiting bene ts of the digital circuits and systems, these bene ts are scaling, di erent and easier adaptation algorithms, calibration, recon gurability and noise immunity. The ADC-based equalizer is designed and post-layout-simulated in a 65-nm CMOS technology. It consumes 15.5 mW in the ADC and 0.57 mW in the discrete-time linear equalizer from a 1-V and 1.2-V power supplies. Low power consumption is achieved by using time-interleaving in the ADC architecture, utilizing charge-steering concept, sharing single reference ladder across the four interleaved channels of ADC, and introducing a novel proposed design for the comparator itself in the Flash analog to digital converter besides using the novel discrete-time linear equalizer circuit.