الفهرس 
oltage Controlled Oscillator Based Analog-to-Digital Converter
System Modeling and SNDR Limitation for the VCO-Based ADCOnly 14 pages are availabe for public view
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Abstract
In future technologies with low supply voltages and low beadroom, the design of conventional voltage-based ADC is facing more difficulties due to the reduced voltage swing. On the other hand, the time resolution and the switching speed are improved. This makes the all digital YCO-Based ADC that utilizes the improved gate delay as its resolution more attractive in deep submicron technologies.
A programmable SWC-based YCO linearization feedback loop was proposed. Thorough analysis has led to clear guidelines for the choice of loop parameters. The main advantage of this linearization scheme is its programmability which makes this technique a suitable candidate in many applications. The loop was able to enhance tbe YCO linearity by a factor of 20. Also resolution enhancement techniques were invoked to improve the ADC resolution.
A nine-bit YCO-based ADC was implemented in the 130 nm CMOS process where the proposed programmable SWC-based YCO linearization technique was applied for SNDR enhancement. The proposed ADC employs a differential YCO coupling technique to
enhance the YCO time resolution. The ADC can operate at sampling rates ranging from 130 ,~
MHz to 280 MHz with nominal sampling rate at 200 MHz. The 200MHz ADC was implemented in 130nm CMOS process showing an SNRJSNDR ranging from 9IA/88.3dB
to 54.3/41.2dB for an input bandwidth of 500kHz - 100MHz while consuming a total of
8.3m W from a 1.2Y supply. The loop improves the YCO linearity from 2% to 0.15%.