الفهرس 
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Abstract
Most digital systems in use today are built in a synchronous manner. A global clock signal passes through the whole chip. However, as digital designs grow fast in size and complexity, it is becoming more and more difficult to provide a unified and accurate clock to the whole system. The clock distribution network is becoming a big headache for designers as it becomes more and more difficult to deal with large variations in clock signal arrival times at different locations in the chip. In order to avoid these problems, the concept of Globally Asynchronous Locally Synchronous (GALS) systems was developed. Communication between synchronous modules is usually achieved with asynchronous interfaces known as Clock Domain Crossings (CDC). Therefore, CDC interfaces are used in the proposed design.
This thesis proposes a design of an asynchronous switch interfacing circuit between any number of different local clock synchronous domains. The asynchronous switch will generate a slower clock frequency from different local clock modules and moderate the high rated clock domain to slow down its clock frequency without stopping or pausing any clock of them during the data communication phase.
The proposed design is simulated using the CMOS 45nm technology of STMicroelectronics. The delay time to change the clock frequency is mathematically modeled. It is shown that the switching delay time depends on the number of multipoint communicating domains. The proposed system is designed to use.