الفهرس 
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Abstract
The rapid evolution of digital systems technology arises the necessity of using fault-tolerant computing. Highly reliable systems design is necessary in the critical operating systems such as: air traffic systems, nuclear power facilities and medical life-support devices, where faulty operation could cause menace to the life. Likewise, unmanned satellites and deep-space probes once launched in the space require maintenance-free circuit.
Static RAM field programmable gate arrays (SRAM FPGAs) devices are engaging in the utilization of designing embedded structures. The most attractive merit of SRAM-based FPGA is its flexibility, since we can reconfigure and reprogram the device or part of it in a little period and on-line, while the system is operating and in an automatic manner. This permits the implemented design a chance to be updated, upgraded, and changed also remotely.
However, SRAM-based FPGA are highly prone to faults specially when working in severe environment circumstances. Designing a highly reliable system, incorporates the use of fault tolerant mitigation techniques. In this thesis we propose a meta-layer fault tolerant structure for real-time systems. The proposed layers feature is that they are independent of each other. For clarity, we specify an evident interface between the designed layers.
Each proposed layer is designed, implemented on Virtex ML605 board and its operation is observed and verified. Only the recovery layer, its behavior is simulated to test the compatibility between proposed layer and study effectiveness of the system and prove its functionality. Other FPGAs can be used as Altera and Atmel FPGAs.
Using triple modular redundancy in the diagnosis layer provides fault masking for 100% of faults that occur in the hardened partitions with the cost of area overhead and more power dissipation. Then the classification of fault to transient or permanent and correction of them with reconfiguration and relocation respectively, prevent fault accumulation in the different redundant modules. Fault recovery of the masked fault elongates the TMR availability.
The problem is raised when a permanent fault affects a spare partition of the FPGA device where TMR is not used, and we recommend using off-line testing before the relocation of faulty modules into another area. We also run the classifier on different FPGAs showing that optimizing the design to the speed metrics is better than optimizing it for the area. Using recent FPGAs families can increase the maximum used frequency, increase the available capacity for applications designs.