الفهرس 
Flash memory cell sensing techniques
Design and simulations of the di erential approach sense ampli er for time domain sensingOnly 14 pages are availabe for public view
 |  | from | 97 |  |  |
| | | from | 97 | | |
Abstract
A fast sense amplifier (SA) with high resolution is required to face the challenges of sensing techniques in embedded memory systems in micro-controller units (MCU’s). Robustness, speed, area of the SA impact the performance of integrated memories in many applications of the automotive industry (electric and hybrid vehicles). Also, improving the sensing technique of the SA reduces the access time of embedded flash memories. As a result, automotive applications including car safety, comfort electronics, and system security performance are enhanced.
The motivation of this work is to present, compare and analyse performance parameters of time-continuous sense amplifiers for time sensing techniques within non-volatile flash memories. Key benchmark parameters impacting the performance of the comparator design of the SA are speed, gain, offset, power consumption and resolution. Firstly, these variables were reviewed and compared analytically within state-of-the-art sense amplifier designs. The latest memory sensing research
[1] [2] considers the common gate SA approach to deliver the highest performance in the market with 65nm and 28nm technologies. To date, the performance of differential based approach has not been compared to common gate approach using 28nm technology for time sensing techniques.
Secondly, circuit design and simulation results of a time domain sense amplifier based on differential pair approach for multi-level-cell (MLC) embedded memories are presented in 28nm technology. This SA design provides lower sensing delay and higher selectivity for stronger programmed cells compared to the state-of-the-art common gate approach in automotive SA designs when simulated in 28nm technol- ogy [3]. Moreover, additional benefits including offset cancellation, high gain and resolution were achieved.
The work is organised as follows. In Chapter 1, an overview of the flash memory cell basic structure and different sensing techniques will be provided. The advan- tages of time-domain sensing in addition to market-leading time-continuous sense amplifier designs which is the focus of this work will be presented. In Chapter 2, comparative analysis at the system level is undertaken for market-leading sense am- plifier designs in time domain sensing. The relative delay and power consumption of the state-of-the-art SA are compared in 65 and 28 nm technologies. The differential pair approach is identified as having a higher potential for lower delay in compar- ison to the common gate approach in small node 28nm technologies. Chapter 3 outlines design specifications for a differential pair based sense amplifier with offset cancellation technique for robust and reliable SA in 28nm technology.
Chapter 4 describes the methodology for testing the performance of differential pair approach designed in Chapter 3. Firstly, MLC concept, application environment
9
and its biasing techniques are described. The simulation results of the time domain sensing design in 28nm technology are then presented when applying various sense voltage and bit line capacitance. Results indicate that the proposed differential pair based SA operates at high performance with low sense voltage and high bit line capacitance.
Chapter 5 builds on the performance evaluation of the differential pair SA design by adding in comparative simulations between the state-of-the-art common gate sense amplifiers and the proposed sense amplifier in terms of power consumption, selectivity for stronger programmed cells and propagation delay in 28nm technology. The proposed differential based SA design is superior to the state-of-the-art common gate sense amplifiers in terms of delay time with the advantage of high selectivity for stronger programmed cell at the cost of higher power consumption. Th figure of merit of the high performance differential based SA is comparable to that of the common gate based SA.
Finally, Chapter 6 explores future implications of a fast and low power sense amplifiers with the challenges in the automotive industry facing the embedded mem- ories. A brief overview of automotive functional safety security standard ISO62622 with a focus on difficulties facing sense amplifies is presented. Moreover, relative importance of design trade-offs for future designs research of SA using time sensing approaches within the automotive industry are given.