الفهرس 
IntroductionOnly 14 pages are availabe for public view
 |  | from | 143 |  |  |
| | | from | 143 | | |
Abstract
The demand on DC-DC converter increases as the scaling of CMOS technolo- gies into the nanometer scale imposes lower supply voltage than the battery voltage which is defined by its electrochemical properties’ limitations High- efficiency DC-DC converters are needed to extend the battery life This thesis aims to design a high efficiency and a low voltage ripple DC-DC Converter for low-energy wireless applications The proposed converter is implemented using UMC130nm CMOS technology with a new design methodology and startup technique to reduce the power-up consumed energy and the startup time varia- tions The proposed buck inductor peak current is well-controlled at all induc- tance, input, and output voltage range using a simple replica circuit matched to the PMOS switch An automatic background calibration is introduced to sustain converter stability and reduce the regulator voltage ripple across differ- ent load, supply and external components values Simulation results show that the proposed converter minimies ripple magnitude and variations especially at light loads while maintaining good efficiency results Finally, a new FoM is introduced to compare all PFM buck designs