الفهرس 
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Abstract
Today the growth of mobile communication systems is as the speed of light. Every day, the number of people using mobiles is increasing rapidly. In this for coming generation of 5G, Filter Bank Multi-Carrier (FBMC) is the latest modulation technique that would be used to achieve high data rate, to avoid both Inter-Symbol Interference (ISI) and Inter-Carrier Interference (ICI) in addition to it improves the spectral efficiency. One of its candidate schemes is the Filter Bank Multi- Carrier (FBMC) with Offset Quadrature Amplitude Modulation (OQAM). This scheme is not only suitable for providing higher data rates but also for having a better spectral efficiency. However, it requires a higher implementation complexity than the current systems. This thesis constitutes an experience of prototyping FBMC/OQAM scheme for a Field Programmable Gate Array (FPGA) based platform in order to deal with such a complexity problem. FPGAs provide a good development platform as they present a good relationship between their processing power, flexibility, and power consumption. As a consequence, they are seen as a good platform for the development of a hardware implementation of baseband processors, as is the case. Therefore, the goal of this thesis is to develop and validate an FPGA implementation of a baseband processor for FBMC transmitter. With this target in mind, a study of the current state of the art is done, assessing several architecture proposals and their results. from the information yielded by this study, the architecture to be implemented was chosen. Once implemented, the developed system is validated through a comparison with existing software simulators.