الفهرس 
IntroductionOnly 14 pages are availabe for public view
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Abstract
The thesis is divided into five chapters besides the list of contents, figures, tables
and list of references.
Chapter 1:
In this chapter, an introduction that discusses the drives and motives behind Giga-
hertz Data Converters is presented. Interesting propoerties of time-based analog
to digital converters are then discussed. Next, the objectives of this thesis and its
contributions are demonstrated.
Chapter 2:
In this chapter, a brief qualitative and quantitative analysis of VCO-based ADCs
is presented. Several VCO-based ADC architectures that address the VCO non-
linearity issue are then discussed, highlighting their respective advantages and
disadvantages.
Chapter 3:
Chapter 3 proposes a new architecture that addresses the VCO non-linearity issue
in an open-loop fashion. It utilizes the conventional two-step residue cancelling
technique presented in prior art. Qualitiative and quantitative analysis of the pro-
posed system and the associated non-idealities are presented to verify the validity
of the proposed architecture, supported by behavioral simulation results.
Chapter 4:
Chapter 4 discusses circuit design of the proposed architecture. It explores imple-
mentation of each building block, along with simulation results for each block and
for the complete architecture.
Chapter 5:
Chapter 5 summarizes the thesis and focuses on its contributions and outcomes.
It concludes the thesis with suggested future work.