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العنوان
Modeling of silicon on insulator devices /
المؤلف
Mahmoud, Eman Mahmoud EL-Damarawy.
هيئة الاعداد
باحث / إيمان محمود الدمراوى محمود
مشرف / صلاح صبرى أحمد عبية
مشرف / محمد فرحات عثمان
مشرف / أحمد محمود هيكل
مناقش / قرنى رجب محمود
مناقش / نهال فايز عريض
الموضوع
Electrical engineering. Silicon-on-insulator technology. Plasmons.
تاريخ النشر
2020.
عدد الصفحات
online resource (118 pages) :
اللغة
الإنجليزية
الدرجة
ماجستير
التخصص
الهندسة الكهربائية والالكترونية
تاريخ الإجازة
1/1/2020
مكان الإجازة
جامعة المنصورة - كلية الهندسة - Department of Electronics & Communication Engineering
الفهرس
Only 14 pages are availabe for public view

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Abstract

Silicon on Insulator (SOI) has played an important role in many applications. This platform is very compatible with the mature complementary metal-oxide-semiconductor (CMOS) fabrication technology which allows large production at a lower cost, as well as a convenient hybridization with electronics. Through the thesis, a novel design is proposed for DNA hybridization detection. The suggested design depends mainly on V-groove structure which confine the light inside the slot region at a wavelength of 1550 nm. Adding a plasmonic layer will be also studied to increase the light inside the slot region and to detect DNA hybridization process. Finite difference element method is used to study the properties of the proposed design. It is found that the power confinement and PD of the V-groove slot waveguide is higher than those of the other designs. However, the modified V- design is easier for real implementation. Further, the addition of plasmonic layer increases the light confinement in the low index region with high potential for DNA hybridization detection with good confinement through the slot region. SOI is polarization dependent. Polarization filter and polarization rotator are the most important devices to solve polarization dependence problem. In this thesis, ‘TM pass polarizer’ is presented and analyzed based on the silicon on sapphire (SOS) platform. It has the same principle as SOI platform and replacing the upper layer of silicon by a sapphire layer. Alternative materials like AZO and ZrN will be used to increase the losses of the Transverse Electric (TE) mode with reduced losses in the Transverse magnetic (TM) mode. It achieves high ER and low IL using bi-metallic plamonic layer (AZO, ZrN). The suggested design has 25.54 dB ER and 0.31 IL at 2µm device length at 2µm wavelength. Additionally, the proposed design has advantages in terms of compactness and compatibility with standard CMOS technology. This design provides easy fabrication process for plamonic devices where high ER and low IL are achieved.