الفهرس 
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Abstract
Synthetic Aperture Radar (SAR) is a main source in remote sensing field. The SAR images used for mapping and identification of target.
Targeting based missions is depending on a high dynamic range images that are caused by some bright objects and some low scattering coefficients. These images are represented in a huge data size that need to be stored onboard or transmitted as a digital signal to the ground station via downlink to be processed in a very short period of time to reduce the warning time for hostilities.
Therefore, compression algorithms are considered an effective solution for SAR design. SAR systems needs simple algorithms due to the low computational requirements; applying compressed sensing in the compression of SAR images can be considered an attractive opinion.
This thesis addresses the problem of the onboard storage and transmission links capabilities (downlink bandwidth) of the huge amount of image data produced by the SAR systems. Four objectives are considered:
1- Using the Compressive Sensing Solution for compressing SAR data, based on the Orthogonal Matching Pursuit (OMP) algorithm for reconstructing compressed data using Matlab software.
2- Deign a pipelined processing system to improve the performance of the OMP and speed up the processing procedures.
3- Design a new adaptive OMP algorithm based on signal threshold calculation to enhance the computational complexity.
4- Implementation and realization of the CS compression module to compress the SAR image/data by using the “Spartan-3A/3AN FPGA Starter Kit”. Hardware-based solutions are considered due to real time nature of the mission.
The reconstructed images produced by the proposed algorithm is evaluated by the Mean Square Error (MSE), Relative Error (RE) and Peak Signal-to-Noise Ratio (PSNR) compared with a well-known compression algorithms (e.g. BAQ, WPT and AP).
This work is implemented using MATLAB® software, Also a hardware design and realization of the CS SAR data compression module is implemented using “Spartan-3A/3AN FPGA Starter Kit.