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Abstract Abstract The advances in consumer electronics and wireless communication impel the eager need for smaller, faster and ultra-low power digital electronics than ever before. Convention low power methods (i.e., voltage scaling, transistor sizing reduction, pipelining and parallelism, etc.) may not be sucient for portable gadgets and medical electronics, where ultra-low power consumption is the primary requirement. To cope with this insuciency, the design of digital sub-threshold logic has been widely investigated. However, robustness issues, in the sub-threshold region, need to be addressed due to the severe delay uncertainty associated with Process, Voltage, and Temperature variations. Asynchronous quasi-delay-insensitive (QDI) circuits are a promising solution to cope with those variations by gracefully accommodating gate and wire delays at the expense of logic redundancy; and therefore, area overhead. To ensure the robustness and design simplicity, we adopt the QDI asynchronous style NULL Convention Logic (NCL). Then, to overcome the area-overhead, we propose a custom direct-circuit approach to design NCL Boolean gates with the minimum area without power or delay penalties. Next, we modify the proposed circuit design to be incorporated in multi-threshold fine-grained pipelines to achieve ultra-low power with high throughput and reduced area. All NCL designs presented in this thesis —including (Koggy-Stone and Ripple-Carry adders) —are compared with the state-of-art NCL designs using Cadence ICFB analog simulators and TSMC 65nm process design kit. from the simulation results, the proposed circuits oered from a significant area-reduction without compromising the power or the delay. Keywords: Ultra-Low Power; Sub-Threshold, Multi-Threshold; Power Gating, Asynchronous Circuits; Null Convention Logic; Dual-Rail Koggy-Stone Adder, Dual-Rail Ripple-Carry Adder, Dual-Rail Boolean Gates. |