الفهرس 
6GB / S serial link transceiver for NOCS
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Abstract
The design of a 6 Gb / s serial link for CUSPARC NoC is presented. The proposed SerDes consists of a serializer and a deserializer. The design targets TSMC digital 65 nm CMOS technology and 1.2-V supply. The use of serial links reduces the interconnect area of the network on chip by 93.96% relative to the design with parallel 32 bit data links. The traces between the cores achieved maximum tolerable clock skew between the Tx and the Rx up to ± 36% of the clock period. The link consumes 6.9 mW power 1.15 pJ / bit