الفهرس 
IntroductionOnly 14 pages are availabe for public view
 |  | from | 250 |  |  |
| | | from | 250 | | |
Abstract
Real Number Modelling (RNM) has become more common as a part of mixed-signal SoC validation. The thesis illustrates modelling Phase Locked Loops (PLL) using SystemVerilog-Real Number Modelling (SV-RNM) as it’s one of the essential blocks and a feedback loop system. It uses the PieceWise Linear (PWL) technique to model the loop filter with higher orders, higher than a first order LPF. The PWL technique needs both the value and the slope information so that the values between the samples can be interpolated, this is represented by User-Defined Type (UDT) and Net (UDN). A fractional divider is modelled using the Sigma-Delta modulator of the MASH 1-1-1 topology to generate the fractional part. Modelling non-linear effects like the phase noise of each sub-block, which is converted to the RMS-jitter (seconds), by using the class datatype that takes complex variables of real and imaginary values then returns some functionalities on these complex variables. Moreover, the loading effect due to capacitances and resistances at the output using User-Defined Resolved Nets (UDRN). The simulation results ensure that the accuracy improvement in the expected outputs of the PLL compared to the outputs from the transistor level with a much faster simulation time as an event-driven simulator is used. A comprehensive functional verification from Constrained Random Verification (CRV), functional coverage, assertions/checkers, and Universal Verification Methodologies are introduced to ensure that these methods can provide a high precious verification environment to analog mixed model DUTs, without waiting until finishing the modeling of analog blocks as a transistor level to verify your system design. Therefore, the RNMs provide very high accuracy of modelling Analog Mixed DUTs, verification methods to ensure the functionality of the system, and stay within the digital simulation environment. Hence, RNM enables SoC-level regressions to cover full-chip functionality while maintaining the high simulation performance.