الفهرس 
Introduction to Hardware Design VerificationOnly 14 pages are availabe for public view
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Abstract
”Python has the Capacity and ecosystem to solve the modern verification challenges” [1].
As hardware designs become more intricate, the need for efficient verification methodologies grows. The conversation about hardware verification being a bottleneck and a
time-consuming task dates back to as early as 1999. Verification techniques have advanced along with the level of design abstraction and have kept up with the complexity
of the implemented designs. When design shifted from being done at the mask level to
RTL and standard cells, Verification also followed along moving from gate-level simulations to transaction-level testbenches using bus functional models. During the journey
of advancement from netlist simulation to verification languages and methodologies, the
focus was on the ”Domain Specific Language” direction with UVM today being the most
used verification methodologies. Today we are witnessing the introduction of Python
(Dynamic High-level programming language) as an alternative to SystemVerilog; due to
its large ecosystem and ease of learning and writing. In this thesis, we explore the process of writing a Python-based testbench, through writing DRAM Memory Controller
testbench. The testbench is implemented using the pyuvm methodology on top of Cocotb that is used to interact with the DUT and to be able to simulate the DUT. The
motivation behind this thesis is twofold: First, we seek to explore Python’s capabilities
in the context of hardware verification. Second, we compare and contrast Python-based
test-benches with the traditional SystemVerilog and UVM approaches. What similarities
do they share? where do they diverge?