الفهرس 
IntroductionOnly 14 pages are availabe for public view
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Abstract
The local oscillator used in radio transceivers generates analog frequency signals. The recent communication systems using spread spectrum such as frequency hopping require a precise and fast frequency reference. Direct Digital Frequency Synthesizers (DDFS) are met the requirements and insensitive to any variations too. In addition, they maintain exact 90 degree phase difference between the I and Q components of the quadrature signal in high bandwidth telecommunication. Nowadays, the digital oscillator is Lock-Up Table (LUT) called DDFS. This synthesizer was first introduced by Tierney et al. in 1971[20]. The basic form of synthesizer consists of a phase accumulator which is used to store Phase angles then, a phase to sine amplitude can be obtained using Read Only Memory (ROM). Finally, the sine amplitudes are applied to Digital- to- Analog Converter (DAC) with low pass filter (LPF). Because of the ROM size grows exponentially with the width of the phase accumulator, the researchers efforts have been proposed to limit the size of ROM. Currently, another method has been used piecewise continuous polynomials to obtain the first quadrant of the sine function without effecting on performance. This thesis introduces a new architecture design for Direct Digital Frequency Synthesizer, the design is developed using top-down design flow from behavioral modeling down to the implementation process. The proposed architecture is intended for use in spread spectrum such as, frequency hopping transceiver and any other digital transceiver and aims to reduce the frequency switching time of the synthesizer and reduce power consumption of synthesizer compared to conventional designs. In order to avoid the high power consumption, no ROM is used but piecewise linear approximation is employed. The proposed architecture has been designed, simulated and synthesized using Mentor Graphics (FPGA Advantages Package). The system is implemented using (XC4010xl) FPGA from XILINX company FPGA with 3.3v supply voltage. The power consumption is 0.396 W at 10MHz clock frequency. The Spurious-Free Dynamic Range (SFDR) is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz. A second order active low pass filter using sallen-key architecture and using switched resistor technique is designed using Pspice on 0.8 m CMOS technology. This thesis will include an introduction to the basic DDFS architecture and explain the modification added to the conventional DDFS to improve its performance. Also it explains the types of frequency synthesizer in modern transceivers.