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Abstract Instruction-level Parallelism ( ILP ) in Supershalar architectures makes use of deep pipelines in order to execute multiple Instructions per cycle . The frequency and behavior of Branch Instructions seriously affect performance of ILP processors . the Performance of branch prediction techniques is evaluted in this thesis . These techniques depended mainly on the speculative execution of Branch Instructions . Various mechanisms both at the complier as well as the processor level have been propsed to predict the branch behaior . in this work , Various branch predictor at processor level have been investigated to do afaircomprison among them A practical implementationis described using several SPECint00 and SOECfp00 benchmarks and similar key parameters for evaluting these predictors.The Performance impact of branch misprediction branch prediction accuracy , the predictor size and history register length have been investigated . |