الفهرس Only 14 pages are availabe for public view
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Abstract
This thesis demonstrates the design of a Clock and Data Recovery circuit (CDR) used in the High Speed serial link transceivers for multi-standard systems. The thesis presents different implementations of CDR circuits, It demonstrates the theory of the selected topology, Analog Phase Interpolation CDR, and the deign of each block used in the design.
This thesis presents a detailed study and design of a clock and data recovery circuit using phase interpolator, for 2.5Gbps to 3.2Gbps. The clock and data recovery circuit is implemented in a 0.13?m CMOS process
Thesis Outline:
Chapter One: It begins with the motivation of the thesis. Then, introducing concept of high speed serial-links.
Chapter Two: An introduction Clock and Data Recovery circuits is presented, Different architectures are introduced, then general considerations and jitter parameters is discussed in CDR circuits.
Chapter Three: CDR system design, that by choosing the system parameters and the selected architecture, analysis and system simulation are also discussed.
Chapter Four: The design of CDR circuit blocks that was used to implement the CDR.
Chapter Five: In this chapter, the implementation of a the system is.
Finally, the thesis ends by extracting conclusions and stating future work that might be done based on this work.