الفهرس 
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Abstract
The proliferating microelectronics industry is challenge by the requisite of innovative test technologies to provide high quality, low cost defect detection methodologies. Traditionally, testing of analog circuits is performed by measuring each parameter in their performance parameter set and comparing it against the tolerance bounds specified by the circuit designer. Devices that fall inside the tolerance limits are classified as defect free and those that fall outside are identified as outliers or defective. This type of test method is generally referred to as functional or specification based testing.
Analog device testing inherently faces a greater set of challenges as compared to digital circuit testing. This can be attributed to : Analog circuit operation is highly dependent on the interaction between various circuit companents, parameters, and so on.
The analog chips or subsystems are more input/output limited than digital ICs.
The continuous nature of the signal sensitive to the entire transfer function of the system.
The variability of functional characteristics of analog circuits due to component variations in processing parameters complicates the testing problem. The goal of an analog test generation methodology is to find a set of test signal attributes that maximize the effect of a targeted specification on a measureable output signal.
In this thesis, an integrated high level analog test generation and fault simulation tool is presented. Test generation aims at determining the attributes of test signals and measurement methodology for a given set of circuit specification.
This thesis represents different techniques with new methodology based on genetic algorithms to detect faults in analog circuits. The minimum set of input patterns to detect all defined faults is determined for testing analog circuits. The goal of our techniques is to optimize the difference of the rwo responses of golden and faulty circuit. For nonlinear circuit, a proposed technique based on the quasi-impulse response QIR and/or the step response SR signatures is presented.The simulation results show that, these techiques can achieve 100 % fault coverage of any circuit.