الفهرس 
IntroductionOnly 14 pages are availabe for public view
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Abstract
In recent years the number of custom designs using FPGA technologies has multiplied. This has led to the development of designs in high level description language like VHDL or Verilog, which allow the designer to conceive the design at the level of RTL without reference to the designer to conceive the design at the level of RTL without reference to the final process has created a market of IPs or complete pre-designed and tested macro-cells which can be incorporated within the designer`s project hierarchy.
On the other hand, the family of ARM processors has experienced a massive growth, not only in the technology but also in their commerical success especially as an embedded controller.
Although the use of a processor core by vendors IP is available, it may cost much, cause the problem of a right modification of the source codes or bring about unsuitability of the interface. Therefore, it is difficult to employ the commerical core for research or education, for example at university. Since the most commom element is designs is a processor core. One, which has a flexible interface and is reusable with open source codes, is desirable to reduce the development period and costs.
In this study, a fully pipelined general purpose ARM processor, which is suited to embedded systems, is developed. it is desired to support research, development and education by opening the source codes. The logic description of the processor is based on VHDL. Therefore, this processor can be applied to design tools of many eda vendors and can be easily reused.