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Abstract
This research studies BPΣΔ modulator as the method of choice for implementing
high-frequency, narrowband ADC. The 4th-order BPΣΔ implemented in this work
digitizes a 200 kHz bandpass signal centered at 10.7 MHz. Clocked at 21.4 MHz in
a double-sampling scheme, it achieves more than 52 dB SNDR, 58 dB SNR, and
suppresses the undesired image component by over 70 dB.
The work emphasizes the ability of circulating delay-type resonator structure for
high speed, low power operation. It proposes a practical methodology for systemlevel
verification on MATLAB, including generic and fast set of SIMULINK ΣΔ
blocks models. Circuit level implementation features a high performance boostedgain
fully-differential folded-cascode opamp with an enhanced SC-CMFB to
support double-sampling requirements.