الفهرس 
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Abstract
In this thesis, an Enhanced Triple-DES Algorithm based on Cluster LUT (Look Up Table) and Pipelining (ETDES) is proposed, as a modification of the Triple DES. ETDES algorithm uses Cluster LUT in hardware implementation and the large embedded memories available in the SPARTAN-E FPGA as hardware designed to obtain a reduced resource utilization. Using cluster LUT can diminish the power consumption by reducing the number of registers and slice/area used for Spartan Xilinx FPGA. In addition, ETDES uses pipelining technique which increases the processing rate. The experimental results are based on simulated and synthesized (Xilinx Spartan–E) using ModelSim 6.5 and VHDL code. The final results show high throughput/area FPGA implementation. The simulation results also prove that the proposed FPGA implementation of ETDES algorithm has better speed performance compared to previous hardware or software implementations. The proposed ETDES implementation decreased the number of slices used due to the pipelining approach and cluster LUTs used. The results also show that the throughput is increased by 50% over CAST implementation [54] and by more than 12% over Rouvery [45], and is almost 10 times compared with GAJ implementation [62].