الفهرس 
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Abstract
Wireless Body Area Network (WBAN) is a propitious new technology, which enables the community to deliver healthcare services to patients and aging people in outback areas. WBANs consist of resource-limited nodes that make reducing power consumption one of the most important challenges. In addition, security of patients’ vital data is very important since any minor modification may threaten patients’ life. This thesis proposes a low-power and efficient architecture design of a narrowband physical layer baseband transceiver for WBANs at 2.4 GHz band. The proposed design targets high data reliability with scalable data transmission rates. Low-cost adjustable data rate modulation/demodulation architectures are proposed with a maximum data rate of 971.4 kbps at 6 MHz clock rate. A digital timing synchronization scheme is also proposed, which can achieve coarse and fine-timing synchronization. Moreover, a low-complexity Phase Error Correction algorithm is proposed with a low-cost pulse deshaping matched filter, to enhance the reliability of the proposed receiver. The proposed baseband transceiver was implemented in 130 nm CMOS technology with 1.2 V power supply. The proposed design consumes 402.54 µW for 971.4 kbps with 6 MHz clock rate. The overall Packet Error Rate for the proposed transceiver is about 1% at Signal-to-Noise Ratio of 9.6 dB. The need for a robust and lightweight security system in WBANs is increasing. Therefore, the thesis proposes a lightweight hybrid cryptography system that depends on chaotic maps with a high degree of non-linearity to resist Crypt-analysis attacks. We combine a stream cipher with a block cipher, which uses a Cipher-Block Chain mode, to enhance the security of the transmitted data with no additional redundancy bits to the original data. Moreover, we use sharing and reusing strategy in hardware to reduce the used resources and the power consumption. We design a block cipher based on Feistel Function with substitution boxes based on chaotic maps to eliminate the need for memory space. Cryptanalysis results show a sufficient robustness, for six rounds of the block cipher. The implementation results demonstrate an 87% resources reduction comparing to AES. The area of the whole system is 387 Gate Equivalent, and the throughput is 266.67 kbps at 100 KHz clock frequency.