الفهرس 
Chapter 1Only 14 pages are availabe for public view
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Abstract
The key target of telecommunication systems for the near future is “Information Available at Any Place, at Any Time and In Every Possible Form”. In order to achieve this target, a unified global system of personal terminal stations must be available. In all cases, low cost and low-power terminal devices are demanded in order to make the services accessible to the public. Driving demands of equal importance are the reduction in volume, weight, and the increase in battery life. To address these demands, recent research has been focused toward the development of a monolithic transceiver using a low-cost CMOS technology. Advances in CMOS technology, however, are driving the operating voltage of integrated circuits increasingly lower. As device dimensions shrink, the applied voltages will need to be proportionately scaled in order to guarantee long-term reliability and manage power density. A single-chip CMOS transceiver requires the exploration of new systems and circuit design techniques which facilitate the highest levels of receiver and transmitter integration. A single future portable communication system may well require the ability to utilize both the services provided by multiple RF standards and the flexibility afforded through multimodal operation. This consequently will demand the capability by a single transceiver to operate on standards with various carrier frequencies, channel bandwidths, sensitivity, and selectivity requirements. The increased functionality offered by a large high-integration system will be well suited to address the needs of a multi-standard transceiver. This thesis introduces a survey of the different types of the most recent low-power communication circuits that can be implemented in VLSI technology. As an application in one of these communication systems, we are concerned with the design of an analog programmable, low noise, low-power, low-voltage, continuous-time baseband filter. This baseband filter will be used in the direct conversion (homodyne) receiver architecture and is designed to meet the baseband signal specifications required for both the Digital Enhanced Cordless Telecommunications (DECT) and the cellular (GSM, PCS-1900, DCS-1800) standards. The baseband filter precedes the analog-to-digital converter (ADC) in the baseband section of an integrated wireless receiver. It must satisfy some exact requirements. The first and most important is selectivity. A filter with a sharp cutoff should select the desired channel and attenuate all other adjacent users. An active implementation of the filter must itself be low noise so as not to degrade the overall receiver noise figure, and it must have wide dynamic range so that out-of-band interferers, prior to filtration, do not create intermodulation distortion which falls in the passband. The same filter can be used to perform anti-aliasing, accommodate for gain variation in the RF front-end and reduce dynamic range requirements of subsequent baseband blocks. The continuous-time baseband filter includes a fixed gain amplifier stage, a variable gain amplifier (VGA) stage, a 7th order low-pass filter and a buffer that drives the sampling network of the ADC. The 7th order filter is designed by combining a simple RC network to employ a single pole after the mixer and a sixth-order filter implemented with the Sallen-Key filter configuration. The baseband filter is designed in a 0.8-µm CMOS technology using the SPICE program. To verify our results, the same baseband filter is redesigned in 0.35-µm CMOS technology and then simulated using the Mentor Graphics Tools. The simulation results obtained for this baseband filter are in good agreement with the overall filter requirements and specifications.